Memory Controllers for Mixed-Time-Criticality Systems

Memory Controllers for Mixed-Time-Criticality Systems

Author: Sven Goossens

Publisher: Springer

ISBN: 9783319320946

Category: Technology & Engineering

Page: 202

View: 844

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This book discusses the design and performance analysis of SDRAM controllers that cater to both real-time and best-effort applications, i.e. mixed-time-criticality memory controllers. The authors describe the state of the art, and then focus on an architecture template for reconfigurable memory controllers that addresses effectively the quickly evolving set of SDRAM standards, in terms of worst-case timing and power analysis, as well as implementation. A prototype implementation of the controller in SystemC and synthesizable VHDL for an FPGA development board are used as a proof of concept of the architecture template.

Memory Controllers for Mixed-Time-Criticality Systems

Memory Controllers for Mixed-Time-Criticality Systems

Author: Sven Goossens

Publisher: Springer

ISBN: 3319811967

Category: Technology & Engineering

Page: 202

View: 497

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This book discusses the design and performance analysis of SDRAM controllers that cater to both real-time and best-effort applications, i.e. mixed-time-criticality memory controllers. The authors describe the state of the art, and then focus on an architecture template for reconfigurable memory controllers that addresses effectively the quickly evolving set of SDRAM standards, in terms of worst-case timing and power analysis, as well as implementation. A prototype implementation of the controller in SystemC and synthesizable VHDL for an FPGA development board are used as a proof of concept of the architecture template.

Distributed Real-Time Architecture for Mixed-Criticality Systems

Distributed Real-Time Architecture for Mixed-Criticality Systems

Author: Hamidreza Ahmadian

Publisher: CRC Press

ISBN: 9781351117814

Category: Computers

Page: 508

View: 893

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This book describes a cross-domain architecture and design tools for networked complex systems where application subsystems of different criticality coexist and interact on networked multi-core chips. The architecture leverages multi-core platforms for a hierarchical system perspective of mixed-criticality applications. This system perspective is realized by virtualization to establish security, safety and real-time performance. The impact further includes a reduction of time-to-market, decreased development, deployment and maintenance cost, and the exploitation of the economies of scale through cross-domain components and tools. Describes an end-to-end architecture for hypervisor-level, chip-level, and cluster level. Offers a solution for different types of resources including processors, on-chip communication, off-chip communication, and I/O. Provides a cross-domain approach with examples for wind-power, health-care, and avionics. Introduces hierarchical adaptation strategies for mixed-criticality systems Provides modular verification and certification methods for the seamless integration of mixed-criticality systems. Covers platform technologies, along with a methodology for the development process. Presents an experimental evaluation of technological results in cooperation with industrial partners. The information in this book will be extremely useful to industry leaders who design and manufacture products with distributed embedded systems in mixed-criticality use-cases. It will also benefit suppliers of embedded components or development tools used in this area. As an educational tool, this material can be used to teach students and working professionals in areas including embedded systems, computer networks, system architecture, dependability, real-time systems, and avionics, wind-power and health-care systems.

Cyber Physical Systems. Design, Modeling, and Evaluation

Cyber Physical Systems. Design, Modeling, and Evaluation

Author: Roger Chamberlain

Publisher: Springer

ISBN: 9783030179106

Category: Computers

Page: 159

View: 114

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This book constitutes the proceedings of the 7th International Workshop on Design, Modeling, and Evaluation of Cyber Physical Systems, CyPhy2017, held in conjunction with ESWeek 2017, in Seoul, South Korea, in October 2017. The 10 papers presented together with 1 extended and 1 invited abstracts in this volume were carefully reviewed and selected from 16 submissions. The conference presents a wide range of domains including robotics; smart homes, vehicles, and buildings; medical implants; and future-generation sensor networks.

Heterogeneous Computing Architectures

Heterogeneous Computing Architectures

Author: Olivier Terzo

Publisher: CRC Press

ISBN: 9780429680038

Category: Computers

Page: 315

View: 897

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Heterogeneous Computing Architectures: Challenges and Vision provides an updated vision of the state-of-the-art of heterogeneous computing systems, covering all the aspects related to their design: from the architecture and programming models to hardware/software integration and orchestration to real-time and security requirements. The transitions from multicore processors, GPU computing, and Cloud computing are not separate trends, but aspects of a single trend-mainstream; computers from desktop to smartphones are being permanently transformed into heterogeneous supercomputer clusters. The reader will get an organic perspective of modern heterogeneous systems and their future evolution.

Architecture of Computing Systems -- ARCS 2016

Architecture of Computing Systems -- ARCS 2016

Author: Frank Hannig

Publisher: Springer

ISBN: 9783319306957

Category: Computers

Page: 402

View: 865

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This book constitutes the proceedings of the 29th International Conference on Architecture of Computing Systems, ARCS 2016, held in Nuremberg, Germany, in April 2016. The 29 full papers presented in this volume were carefully reviewed and selected from 87 submissions. They were organized in topical sections named: configurable and in-memory accelerators; network-on-chip and secure computing architectures; cache architectures and protocols; mapping of applications on heterogeneous architectures and real-time tasks on multiprocessors; all about time: timing, tracing, and performance modeling; approximate and energy-efficient computing; allocation: from memories to FPGA hardware modules; organic computing systems; and reliability aspects in NoCs, caches, and GPUs.

Performance of Time-Critical Embedded Systems under the Influence of Errors and Error Handling Protocols

Performance of Time-Critical Embedded Systems under the Influence of Errors and Error Handling Protocols

Author: Philip Axer

Publisher: Cuvillier Verlag

ISBN: 9783736981973

Category: Technology & Engineering

Page: 218

View: 899

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As for the entire embedded-systems domain, the complexity of safety-critical systems is growing rapidly. Additionally, the rate of errors in such devices also increases for instance due to silicon shrinking. Hence, error-free operation under in-specification operating conditions cannot be assumed for next-generation safety-critical devices. As a rule of thumb the key design parameters for such systems performance, price and reliability are almost always contradicting design goals. This work addresses the related design space, highlights the challenges and discusses the trade-offs. Of unique interest is the reliability under real-time aspects. Naturally, there are error-handling protocols, error-correcting codes, and modular redundancy available. However, the effect of errors always has an influence on system timing. Even if an error is handled and corrected, it remains unclear under which situations timing requirements are met. This leads to the absurd situation that a device such as an advanced driver assistance system produces correct data even under errors but fails to deliver service because hard deadlines are missed. We present the ASTEROID architecture as a next-generation high-performance, real-time platform which addresses reliability and thus safety aspects. ASTEROID differs from other MPSoC platforms in its cross-layer error handling approach. The hardware implements the bare minimum to support the operating system with support for redundant computing, allowing the software to flexibly schedule tasks for redundant or regular execution. This architecture was joint work between TU Braunschweig and TU Dresden. In this work, we present the hardware architecture and discuss the real-time performance under errors in a compositional way. Therefore, we consider errors in communication (be it on-chip as well as off-chip) and errors in the processing core itself. The scientific contributions are first to extend compositional performance analysis (CPA) also by covering error effects, second to cover end-to-end error protocols with CPA, third to provide execution models and analysis for redundant execution and finally to bound the likelihood of timing violations in communication and computation under a given error model. Sowohl eingebettete Systeme im Allgemeinen, als auch sicherheitskritische Systeme im Speziellen werden zunehmend komplexer. Hinzu kommt, dass aufgrund der Verkleinerung der Strukturbreite moderner Halbleiterprozesse die transiente Fehlerrate deutlich ansteigt. Daher kann nicht von einem fehlerfreien Betrieb von zukünftigen eingebetteten, sicherheitskritischen Systemen unter nominalen Bedingungen ausgegangen werden. Als Faustregel kann man zusammenfassen, dass die Schlüsselparameter im Entwurfsraum Performance, Preis und Zuverlässigkeit so gut wie immer widersprüchliche Entwurfsziele sind. Diese Arbeit zielt auf diesen Entwurfsraum ab, zeigt die Herausforderungen und diskutiert die Trade-Offs. Von besonderem Interesse ist die Zuverlässigkeit unter Echzeitaspekten. Selbstverständlich gibt es Fehlerbehandlungsprotokolle, Fehlercodes und modulare Redundanz. Allerdings hat die Korrektur von Fehlern immer einen gewissen Einfluss auf das Zeitverhalten des gesamten Systems. Selbst, wenn ein Fehler korrigiert werden konnte, ist unklar, unter welchen Situationen das Zeitverhalten eingehalten wird. Dies kann zu der absurden Situation führen, dass ein Fehler in einem Fahrerassistenzsystem korrigiert werden kann, dennoch aber das Verpassen einer Deadline zu einem Systemfehler führt. In dieser Arbeit stellen wir die ASTEROID Plattform vor, die im Rahmen einer Kooperation der TU Braunschweig mit der TU Dresden entstanden ist. Diese Plattform ist speziell im Hinblick auf Echtzeitaspekte, Performance, Zuverlässigkeit und damit einhergehend Sicherheit entworfen worden. ASTEROID unterscheidet sich von anderen MPSoC Plattformen durch seinen Cross-Layer Fehlerbehandlungsansatz. Die eigentliche Hardwareplattform implementiert nur das absolute Minimum an Fehlertoleranz, um das darüber geschaltete Betriebssystem zu unterstützen. Dieses übernimmt dann die eigentliche Redundanz und erlaubt damit eine flexible Mischung von redundanten und nicht-redundanten Anwendungen. In dieser Arbeit wird die Plattform in Bezug auf die Echtzeitperformanz unter Fehlern in einer kompositionellen Weise untersucht. Dafür werden Fehlereffekte in der on-chip und off-chip Kommunikation sowie Fehler im eigentlichen Rechenkern selbst betrachtet. Der wissenschaftliche Beitrag dieser Arbeit liegt zum einen in einer generalisierten kompositionellen Performanzanalyse, die zudem Fehlereffekte berücksichtigt. Zum Anderen werden Ende-zu-Ende Protokolle und redundante Anwendungen modelliert und in Bezug auf ihre Echtzeitfähigkeit untersucht. Für viele der genutzten Verfahren wird auch eine Zuverlässigkeitsabschätzung des Echtzeitverhaltens bei einem gegebenen Fehlermodell durchgeführt.

Predictable and Runtime-Adaptable Network-On-Chip for Mixed-critical Real-time Systems

Predictable and Runtime-Adaptable Network-On-Chip for Mixed-critical Real-time Systems

Author: Sebastian Tobuschat

Publisher: Cuvillier Verlag

ISBN: 9783736989795

Category: Computers

Page: 260

View: 968

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The industry of safety-critical and dependable embedded systems calls for even cheaper, high performance platforms that allow flexibility and an efficient verification of safety and real-time requirements. In this sense, flexibility denotes the ability to (online) adapt a system to changes (e.g. changing environment, application dynamics, errors) and the reuse-ability for different use cases. To cope with the increasing complexity of interconnected functions and to reduce the cost and power consumption of the system, multicore systems are used to efficiently integrate different processing units in the same chip. Networks-on-chip (NoCs), as a modular interconnect, are used as a promising solution for such multiprocessor systems on chip (MPSoCs), due to their scalability and performance. Hence, future NoC designs must face the aforementioned challenges. For safety-critical systems, a major goal is the avoidance of hazards. For this, safety-critical systems are qualified or even certified to prove the correctness of the functioning under all possible cases. A predictable behavior of the NoC can help to ease the qualification process (e.g. formal analysis) of the system. To achieve the required predictability, designers have two classes of solutions: isolation (quality of service (QoS) mechanisms) and (formal) analysis. For mixed-criticality systems, isolation and analysis approaches must be combined to efficiently achieve the desired predictability. Isolation techniques are used to bound interference between different application classes. And analysis can then be applied verifying the real-time applications and sufficient isolation properties. Traditional NoC analysis and architecture concepts tackle only a subpart of the challenges—they focus on either performance or predictability. Existing, predictable NoCs are deemed too expensive and inflexible to host a variety of applications with opposing constraints. And state-of-the-art analyses neglect certain platform properties (e.g. they assume sufficient buffer sizes to avoid backpressure) to verify the behaviour. Together this leads to a high over-provisioning of the hardware resources as well as adverse impacts on system performance (especially for the non safety-critical applications), and on the flexibility of the system. In this work we tackle these challenges and develop a predictable and runtime-adaptable NoC architecture that efficiently integrates mixed-critical applications with opposing constraints. Additionally, we present a modeling and analysis framework for NoCs that accounts for backpressure (i.e. full buffers in network routers delaying the progress of network packets). This framework enables to evaluate the performance and reliability early at design time. Hence, the designer can assess multiple design decisions and trade-offs (such as area, voltage, reliability, performance) by using abstract models and formal approaches.

A Journey of Embedded and Cyber-Physical Systems

A Journey of Embedded and Cyber-Physical Systems

Author: Jian-Jia Chen

Publisher: Springer Nature

ISBN: 9783030474874

Category: Technology & Engineering

Page: 176

View: 661

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This Open Access book celebrates Professor Peter Marwedel's outstanding achievements in compilers, embedded systems, and cyber-physical systems. The contributions in the book summarize the content of invited lectures given at the workshop “Embedded Systems” held at the Technical University Dortmund in early July 2019 in honor of Professor Marwedel's seventieth birthday. Provides a comprehensive view from leading researchers with respect to the past, present, and future of the design of embedded and cyber-physical systems;Discusses challenges and (potential) solutions from theoreticians and practitioners on modeling, design, analysis, and optimization for embedded and cyber-physical systems;Includes coverage of model verification, communication, software runtime systems, operating systems and real-time computing.

Commercial Aviation Cyber Security

Commercial Aviation Cyber Security

Author: Terry Lee Davis

Publisher: SAE International

ISBN: 9780768083552

Category: Technology & Engineering

Page: 88

View: 995

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In the next decade, commercial aviation will see Next Generation ATM (NextGEN), Single European Skies ATM Research (SESAR), and others utilizing Internet- based air-to-ground communication links for advanced “air traffic control” (ATC) communications. Commercial Aviation Cyber Security: Current State and Essential Reading highlights some of the major issues the industry must confront if the vision of a new, advanced air traffic management is to come to fruition. This will require standardization work to identify key components with built-in cyber security that will guide prototype testing, functionality, and prioritizing implementation efforts to solve the roadblocks to global interoperability. The ten technical papers selected for Commercial Aviation Cyber Security: Current State and Essential Reading span the last decade’s work in commercial aviation cyber security, and aircraft cyber technologies. Cyber security cannot be “bolted on” as an after-thought as commercial aviation begins to move to the automated management of national airspaces.

Solid-State-Drives (SSDs) Modeling

Solid-State-Drives (SSDs) Modeling

Author: Rino Micheloni

Publisher: Springer

ISBN: 9783319517353

Category: Technology & Engineering

Page: 170

View: 673

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This book introduces simulation tools and strategies for complex systems of solid-state-drives (SSDs) which consist of a flash multi-core microcontroller plus NAND flash memories. It provides a broad overview of the most popular simulation tools, with special focus on open source solutions. VSSIM, NANDFlashSim and DiskSim are benchmarked against performances of real SSDs under different traffic workloads. PROs and CONs of each simulator are analyzed, and it is clearly indicated which kind of answers each of them can give and at a what price. It is explained, that speed and precision do not go hand in hand, and it is important to understand when to simulate what, and with which tool. Being able to simulate SSD’s performances is mandatory to meet time-to-market, together with product cost and quality. Over the last few years the authors developed an advanced simulator named “SSDExplorer” which has been used to evaluate multiple phenomena with great accuracy, from QoS (Quality Of Service) to Read Retry, from LDPC Soft Information to power, from Flash aging to FTL. SSD simulators are also addressed in a broader context in this book, i.e. the analysis of what happens when SSDs are connected to the OS (Operating System) and to the end-user application (for example, a database search). The authors walk the reader through the full simulation flow of a real system-level by combining SSD Explorer with the QEMU virtual platform. The reader will be impressed by the level of know-how and the combination of models that such simulations are asking for.

Architecture of Computing Systems -- ARCS 2014

Architecture of Computing Systems -- ARCS 2014

Author: Erik Maehle

Publisher: Springer

ISBN: 9783319048918

Category: Computers

Page: 245

View: 116

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This book constitutes the proceedings of the 27th International Conference on Architecture of Computing Systems, ARCS 2014, held in Lübeck, Germany, in February 2014. The 20 papers presented in this volume were carefully reviewed and selected from 44 submissions. They are organized in topical sections named: parallelization: applications and methods; self-organization and trust; system design; system design and sensor systems; and virtualization: I/O, memory, cloud; dependability: safety, security, and reliability aspects.